Method and apparatus for testing integrated circuits for susceptibility to latch-up

ABSTRACT

In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respective test block and a plurality of sensor blocks located at successively increasing distances from the respective injector block. Each sensor block includes a PNPN latch-up test structure. The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.

FIELD OF THE INVENTION

This application is a 371 of PCT/IB05/50347 filed on Jan. 27, 2005.

This invention relates to a method and apparatus for testing integratedcircuits for susceptibility to latch-up and, more particularly, to amethod and apparatus for testing CMOS, BiCMOS and bipolar integratedcircuits for their susceptibility to latch-up, so as to obtainmeasurements and extract design rules for reducing or eliminating therisk of latch-up occurring in such integrated circuits.

BACKGROUND OF THE INVENTION

Latch-up is a failure of CMOS, BiCMOS and bipolar integrated circuits(ICs) characterized by excessive current drain coupled with functionalfailure, parametric failure and/or device destruction. Circuits aremanually made in silicon by combining adjacent p-type and n-type regions(i.e. over-seeded or “doped” with appropriate impurities) intotransistors. Paths other than those chosen to form the desiredtransistor can sometimes result in so-called parasitic transistorswhich, under normal conditions, cannot be activated. Latch-up occurs asa result of interaction between the parasitic bipolar transistors alwayspresent in CMOS, bipolar and BiCMOS devices, caused by a spuriouscurrent spike, such that a pair of such parasitic transistors combineinto a circuit with large positive feedback.

Referring to FIG. 1 of the drawings, there is illustrated schematicallya CMOS inverter, and the desired circuit thereof is illustratedschematically in FIG. 2 of the drawings. The parasitic PNP and NPNtransistors form a parasitic PNPN device, in which the collector of theparasitic PNP transistor feeds the base of the parasitic NPN transistor,and the collector of the parasitic NPN transistor feeds the base of theparasitic PNP transistor, as illustrated in the circuit diagram of FIG.3. When latch-up occurs, a positive feedback takes place, causing alarge current flow between the supply voltage line (V_(DD)) and theground line (V_(SS)) of the integrated circuit, causing the circuit ofFIG. 3 to turn fully on and cause a short circuit across the device,thereby preventing correct operation of the IC and causing discharge ofthe supply source or burn-up of the IC. Similar combinations ofparasitic bipolar devices occur also in BiCMOS and bipolar technologies.

The I-V characteristic of the PNPN configuration illustrated in FIG. 3is shown in FIG. 4 of the drawings. When a current larger than thetrigger current, or a voltage larger than the trigger voltage, is fed tothe structure, a snap-back phenomenon occurs in the PNPN parasiticdevice and the current suddenly increases. When the trigger is removed,the high current continues to flow if the holding voltage is lower thanthe IC supply voltage. If the holding voltage is larger than the ICsupply voltage, the IC is said to be ‘latch-up free’, because once theabove-mentioned trigger is removed, the IC continues to functioncorrectly. The trigger stimulus can originate from several differentsources, including, an ESD (electrostatic discharge) pulse during ICoperation, a large current or voltage generated by device switchingduring IC operation, etc. In addition, the trigger current may begenerated within the latching structure (of FIG. 3) or it may begenerated elsewhere in the circuit and propagate to the latchingstructure.

During IC development, it is highly desirable to ensure that anintegrated circuit is latch-up free, or at least that the maximumcurrent that can reach the parasitic PNPN devices in the integratedcircuit is less than the trigger current, in which case, the IC is saidto be ‘latch-up immune’, because latch-up cannot be triggered. Mostmodem technologies, do not tend to be latch-up free, and as such have tobe made latch-up immune.

Typically, integrated circuits are tested for their susceptibility tolatch-up in two ways:

-   -   By applying a voltage and/or current stress to the IC        input-output pins and then verifying whether such applied stress        induces latch-up in the integrated circuit;    -   By measuring the latch up parameters (holding voltage, and        trigger current and voltage) on special PNPN test modules, in        respect of which all diffusions are externally contacted. An        example of such a test module is illustrated schematically in        FIG. 5 of the drawings, and comprises an IC substrate 1, a        P-type well 2 (P-Well), an N-type well 3 (N-Well), a shallow        trench isolation (STI) region (or LOCOS) 4, P-Well and N-Well        contact diffusions 5 and 6 respectively, an N+ diffusion 7 in        P-Well (N+ hot-active), a P+ diffusion 8 in N-Well (P+        hot-active), an inter-level dielectric (ILD) 9 and metal        contacts 10 to the PNPN diffusions.

The first method referred to above allows checking as to whetherlatch-up can be induced in the integrated circuit, having regard to thefact that within given specifications for the maximum stress values, theIC should be latch-up immune. Typically, a current or voltage stress isapplied to the IC pins and it is determined whether or not latch-upoccurs. This method provides an accurate method of checking thesusceptibility of the IC to the occurrence of latch-up, i.e. the risk ofthe occurrence of latch-up in the IC during operation thereof. However,this test can only be applied very late in the IC market introductionflow, at a time when the IC has already been manufactured. In the casethat latch-up occurs (i.e. the IC is determined not to be latch-upimmune), it is not possible to discriminate if latch-up has occurred inthe input-output circuitry or in the IC circuitry providing the chiprequired functions (i.e. the IC core), unless failure analysistechniques are employed. In the event that the design or manufacturingprocess is required to be improved to make the IC latch-up immune, thenat this stage in the market introduction flow, the result is asignificant additional cost in product development and a delay in themarket introduction, which is obviously undesirable and may result inthe IC being obsolete by the time it does reach the market. Furthermore,it is not possible using this method to study how latch-up depends onthe design of the IC and on the manufacturing process (i.e. junctionimplants, STI shaping, etc).

The second method referred to above allows the study of the dependencyof the latch-up parameters on the manufacturing process and designvariables. It is possible to investigate how the latch-up parametersdepend on the design by manufacturing different test modules in whichthe design parameters (such as the distance between hot-actives and wellcontacts, the distance between hot-actives, etc.) are varied. Thedependency of the latch-up parameters on the manufacturing process canbe investigated by running split diffusion lots in which some processparameters are varied. Since the PNPN test structures are standard testmodules that can be manufactured independently of the IC design, thislatch-up study can be performed early in the manufacturing process flowdevelopment, well before an IC is taped out and manufactured.Furthermore, the acquired knowledge can be applied to all subsequent ICdesigns. However, the typical PNPN test structures do not permit studyof the effect of a current or voltage stress applied to the IC pins,since the stress testing is carried out directly on the PNPN by applyinga stress current or voltage to the N+ hot-active 8 and to the P+hot-active 9. As only a fraction of the current injected into the ICpins reaches the IC core, using the typical latch-up PNPN test modulesleads to over-estimates of the maximum current which will actually reachthe IC core. As a consequence, in order to make the IC latch-up immune,unnecessary design rules may be applied, with a resultant negativeeffect on IC performance and an undesirable increase in chip area.

SUMMARY OF THE INVENTION

We have now devised an improved arrangement, and it is an object of thepresent invention to provide a method and apparatus for testingintegrated circuits for their susceptibility to latch-up in whichlatch-up can be tested by applying current and voltage stressesrelatively early in the manufacturing process flow development of thecircuit.

In accordance with the present invention, there is provided a testmodule for testing the susceptibility of an integrated circuit design tolatch-up, the test module comprising a plurality of test blocks,connected in parallel, each test block comprising an injector block forapplying a stress current or voltage to the respective test block, and aplurality of sensor blocks located at successively increasing distancesfrom the respective injector block, each sensor block comprising a PNPNlatch-up test structure.

The present invention further extends to a method of testing thesusceptibility of an integrated circuit design to latch-up, the methodcomprising providing a test module comprising a plurality of testblocks, connected in parallel, each test block comprising an injectorblock for applying a stress current or voltage to the respective testblock, and a plurality of sensor blocks located at successivelyincreasing distances from the respective injector block, each sensorblock comprising a PNPN latch-up test structure, the method furthercomprising applying a stress current or voltage to one or more of theinjector blocks, and obtaining resultant current measurements at one ormore of the respective sensor blocks.

Thus, the present invention provides a method and apparatus for testingthe susceptibility of an IC design, with the following significantadvantages relative to the prior art:

-   -   Latch-up can be tested by conventional current and voltage        stresses, without requiring the existence of an actual product.        As a consequence, potential latch-up issues can be solved before        the product tape-out, thus allowing a dramatic saving in        development costs and time.    -   Contrary to the prior art latch-up test method based on the IC        test described above, in which a dedicated latch-up test system        is required and the IC needs to be packaged, a conventional        parameter analyzer is sufficient to carry out the measurement at        wafer level, as a result of the present invention.    -   Furthermore, it is possible to study the latch-up parameter        dependency on the process and design variables in a design        configuration closely similar to the design of the final IC.        This allows for optimization of IC design, by defining proper        design rules. As a consequence, the IC area can be reduced and        IC performance can be improved, relative to the prior art.

Each test block may be connected to a bondpad, via which a stresscurrent or voltage may be applied to a respective injector block. Theinjector blocks are preferably connected between first and second supplylines, and the sensor blocks are preferably connected between third andfourth supply lines, different from the first and second supply lines,such that the two blocks can be biased independently, and so that adistinction can be made between the operation of the injector blocks andthe sensor blocks during testing Each PNPN latch-up test structurepreferably comprises an N+ and a P+ hot-active, which hot-actives arepreferably connected to respective probe sensor lines. Heating means maybe provided in respect of the PNPN latch-up test structures, and suchheating means may, for example, comprise polysilicon rings surroundingeach of the PNPN latch-up test structures.

The method of the invention may comprise the steps of disconnecting thesensor blocks during application of the stress current or voltage to theinjector blocks, and obtaining current measurements at the injectorblocks so as to determine the susceptibility of the injector blocks tolatch-up.

An injector block and/or a sensor block may be determined to besusceptible to latch-up if a current measurement thereat exceeds apredetermined threshold. Sequential current measurements are preferablyobtained at each PNPN latch-up test structure of a sensor block.Beneficially, each injector block and each sensor block can beindependently biased and, in fact, in one embodiment, each PNPN latch-uptest structure may be independently biased.

These and other aspects of the present invention will be apparent from,and elucidated with reference to, the embodiments described herein.

DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described by way ofexamples only and with reference to the accompanying drawings, in which:

FIG. 1 is a schematic cross-sectional view of an exemplary CMOSintegrated circuit illustrating the parasitic bipolar transistorsresponsible for latch-up;

FIG. 2 is a schematic circuit diagram illustrating the desiredconfiguration of the parasitic bipolar transistors in the arrangement ofFIG. 1;

FIG. 3 is a schematic circuit diagram illustrating the configuration ofthe parasitic bipolar transistors in the arrangement of FIG. 1, as aresult of latch-up;

FIG. 4 is a graphical illustration of the I-V characteristics of thearrangement of FIG. 3;

FIG. 5 is a schematic cross-sectional illustration of a PNPN test moduleaccording to the prior art;

FIG. 6 is a schematic block diagram of a test chip module according toan exemplary embodiment of the present invention;

FIG. 7 is a schematic circuit diagram of an exemplary I/O block whichcan be used as an injector in the test chip module of FIG. 6;

FIG. 8 is a schematic plan view of a first exemplary sensor block whichcan be used in the test chip module of FIG. 6; and

FIG. 9 is a schematic plan view of a second exemplary sensor block whichcan be used in the test chip module of FIG. 6.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 6 of the drawings, a test chip module according to anexemplary embodiment of the present invention, comprises a plurality ofexternal bondpads 22 connected to respective supply voltage lines 15 andground lines 14, and a series of test points 30 connected in parallel.Each test point 30 comprises a bondpad 11 to which a respective injector12 is connected, and to each injector 12 there is connected a sensorblock 13. The injectors 12 are intended to generate latch-up stress, andthe sensor blocks are for measuring the latch-up susceptibility of thetest module. As will be shown, injectors can also be used to test thelatch-up susceptibility of I/O blocks.

Each injector 12 can simply be a circuit similar to a standard I/O blockused in the eventual IC design, and referring to FIG. 7 of the drawingsa circuit diagram of an exemplary injector design is illustrated. Ofcourse, it will be appreciated by a person skilled in the art that theinjector 12 (or I/O block) can be more complex than that illustrated inFIG. 7, depending on requirements.

By applying a stress voltage or current to the injector bondpad 11, acurrent is dumped on the test chip substrate, which current diffuses tothe respective sensor block 13, where latch-up can be triggered.

A sensor block 13 suitable for use in the present invention may consistof several PNPN latch-up test structures of similar construction to thestructure illustrated in FIG. 5 of the drawings. Such PNPN teststructures are located along the respective sensor block 13 atincreasing distances from the injector 12, in order to allowinvestigation of the effects on latch-up of the distance between the I/Oblocks and the IC core.

FIG. 8 of the drawings illustrates how a sensor block 13 for use in afirst exemplary embodiment of the present invention may be organized.Referring to the drawing, the P-Well and N-Well contacts 5, 6 of eachPNPN test structure are biased by ground 18 and supply voltage 19 lines,respectively, which are different to those used for the I/O blocks ofthe injectors 12, so as to allow the use of different supply voltagesand also to permit distinguishing between the possible occurrence oflatch-up in the sensor blocks or in the I/O blocks. The N+ and P+hot-actives 7, 8 of the sensors are connected to the N+ 16 and the P+ 17probe sensor lines respectively. It will be appreciated by a personskilled in the art that, in order to test for latch-up in respect ofeach of the sensors placed at different distances from the injector 12,different probe lines will need to be used in respect of each of thedifferent PNPN test structures of a sensor block 13.

Thus, by placing in parallel a set of injector-sensor block couples suchas the injector-sensor block couple shown in FIG. 8, as illustrated inFIG. 6, it is possible to investigate the effect on latch-up ofdifferent types of injectors. For instance, the effect of differenttypes of guard-rings or guard-bands can be investigated. Ideally, eachinjector and each sensor would be independently biased and accessed,thereby allowing a full 2D sensitivity picture to be developed. However,in order to save on bondpads and, thus, test-chip area, interconnectionlines can be shared by the injector-sensor block couples. For example,the well contacts of the sensors can share the same supply lines (18, 19respectively for P- and N-Well).

In order to test for the latch-up sensitivity of the I/O blocks, thesensor blocks can be left disconnected during testing. In this case, acurrent or voltage stress can be applied to the injector bondpad and thelatch-up occurrence can be verified by measuring the current flowing tothe injector ground and supply voltage lines.

In an alternative structure for the sensor block, as illustratedschematically in FIG. 9 of the drawings, polysilicon rings 20 can beplaced around the PNPN test structures. Polysilicon rings 20 act asheaters with respect to the PNPN test structures, thus allowing latch-upat high temperatures to be tested, without the requirement for anexternal heating source. Similarly, polysilicon rings can be placed inrespective I/O blocks to increase injector temperature during testing.

Thus, the latch-up test chip described above is a compact latch-upanalysis vehicle that merges the easy testability of the typical PNPNlatch-up test structures with the advantages of the IC latch-up test. Byapplying a current or voltage stress to the injector bondpads, one caninvestigate the latch-up occurrence in the I/O blocks and in the sensorblocks, by simply measuring the current. When the current measured onthe supply voltage or ground lines of the I/O block or of the sensorblock is higher than a predetermined threshold, then latch-up isdetected. The effect of the distance between the sensors and theinjector can be studied by taking sequential measurements at the sensorsplaced at different distances from the injector. During the measurementat each sensor, the other ones are not biased. The effect of the I/Oblock design on the latch-up susceptibility of the sensors can also beinvestigated by sequentially applying the stress to the injectors, whileleaving the sensors unbiased.

Design rules to obtain a latch-up immune IC can be identified by meansof the latch-up test chip. Since the latch-up stresses are performed inrespect of an IC-like design, the resultant design rules are notrequired to be conservative, as would be the case if the simple priorart PNPN test structure described above is used. This is likely toresult in a significant reduction in IC area and an improvement in ICperformance relative to prior art devices. Furthermore, an IC-likedevice can be tested well before the IC tape-out, thereby enabling adramatic cost reduction with respect to IC development whenever latch-upissues are detected, relative to prior art processes.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe capable of designing many alternative embodiments without departingfrom the scope of the invention as defined by the appended claims. Inthe claims, any reference signs placed in parentheses shall not beconstrued as limiting the claims. The word “comprising” and “comprises”,and the like, does not exclude the presence of elements or steps otherthan those listed in any claim or the specification as a whole. Thesingular reference of an element does not exclude the plural referenceof such elements and vice-versa. The invention may be implemented bymeans of hardware comprising several distinct elements, and by means ofa suitably programmed computer. In a device claim enumerating severalmeans, several of these means may be embodied by one and the same itemof hardware. The mere fact that certain measures are recited in mutuallydifferent dependent claims does not indicate that a combination of thesemeasures cannot be used to advantage.

1. A test module for testing the susceptibility of an integrated circuitdesign to latch-up, the test module comprising: a plurality of testblocks, connected in parallel, each test block including an injectorblock for applying a stress current or voltage to the respective testblock, and a plurality of sensor blocks located at successivelyincreasing distances from the respective injector block, each sensorblock including a PNPN latch-up test structure.
 2. The test module asrecited in claim 1, wherein each test block is connected to a bondpad,said stress current or voltage being applied to said injector via saidbondpad.
 3. The test module as recited in claim 1, wherein said injectorblocks are connected between first and second supply lines.
 4. The testmodule as recited in claim 3, wherein contacts of said sensor blocks areconnected between third and fourth supply lines, different from saidfirst and second supply lines.
 5. The test module as recited in claim 1,wherein each PNPN latch-up structure includes an N⁺ and a P⁺ hot-active,which hot-actives are connected to respective probe sensor lines.
 6. Thetest module as recited in claim 1, wherein each of said PNPN latch-uptest structures includes a heater.
 7. A test module according to claim6, wherein said heaters comprise polysilicon rings located aroundrespective PNPN latch-up test structures.
 8. A method of testing thesusceptibility of an integrated circuit design to latch-up, the methodcomprising: providing a test module comprising a plurality of testblocks, connected in parallel, each test block including, an injectorblock for applying a stress current or voltage to the respective testblock, and a plurality of sensor blocks located at successivelyincreasing distances from the respective injector block, each sensorblock including a PNPN latch-up test structure, applying a stresscurrent or voltage to one or more of the injector blocks, and obtainingresultant current measurements at one or more of the respective sensorblocks.
 9. The method as recited in claim 8, further comprising,disconnecting said sensor blocks during application of said stresscurrent or voltage to one or more of said injector blocks, and obtainingcurrent measurements at said injector blocks to determine thesusceptibility thereof to latch-up.
 10. The method as recited in claim8, wherein an injector block or a sensor block is determined to besusceptible to latch-up if a current measurement therein exceeds apredetermined threshold.
 11. The method as recited in claim 8, whereinsequential current measurements are obtained at each PNPN latch-up teststructure of a sensor block.
 12. The method as recited in claim 8,wherein each injector block and each sensor block can be independentlybiased.
 13. The method as recited in claim 12, wherein each PNPNlatch-up test structure can be biased independently.
 14. A test modulecomprising: a plurality of external bond-pads each connected torespective supply voltage and ground lines; a plurality of test pointsconnected in parallel, each of the test points including a bond-pad; aplurality of injectors for applying a stress current or volatge, each ofthe injectors connected to one of the bond-pads of the test points andeach of the injectors connected to the respective supply voltage andground lines of one of the external bond-pads; a plurality of sensorblocks each of which is connected to one of the injectors, each of thesensor blocks including a PNPN latch-up test structure for measuringlatch-up susceptibility of the test module, the sensor blocks connectedto the respective supply voltage and ground lines of another one of theexternal bond-pads.
 15. The test module of claim 14, wherein each of thesensor blocks includes a plurality of PNPN latch-up test structures, theplurality of PNPN latch-up test structures of a respective one of thesensor blocks located at successively increasing distances from theinjector connected to the respective one of the sensor blocks.
 16. Thetest module of claim 15, wherein each of the sensor blocks includes aplurality of polysilicon rings each of which is located around one ofthe plurality of PNPN latch-up test structures, the polysilicon ringsadapted to act as heaters.
 17. The test module of claim 14, wherein eachof the PNPN latch-up test structures includes a P-Well contact that isconnected to the ground line of the another one of the externalbond-pads and an N-Well contact that is connected to the supply voltageline of the another one of the external bond-pads.
 18. The test moduleof claim 14, wherein each of the PNPN latch-up test structures includesN⁺ and P⁺ hot-actives that are connected to respective probe sensorlines.
 19. The test module of claim 14, wherein each of the injectorsincludes a plurality of transistors.